The present invention relates to a packet transmission method and apparatus which can cope with a data transmission packet loss or error.
In an error correction scheme for a conventional fixed-length packet switching system, error correction codes are added in units of packets at most. In many cases, error correction codes are not added to all the data of one packet, but an error correction code is added to a header portion which is an important portion of a packet. In many cases, data are processed in units of packets.
In the error correction scheme for this conventional fixed-length packet switching system, error correction codes are added to data in units of packets. Therefore, this scheme exhibits a correction ability with respect to bit errors in one packet but no effect on a packet loss. Especially in a fixed-length packet switching network such as an ATM (Asynchronous Transfer Mode) switching network, in which no error re-transmission processing is performed, a packet may be lost. For this reason, a communication device demanding high reliability in terms of transmission quality cannot be connected to such a network.
In a data memory monitoring scheme disclosed in Japanese Patent Laid-Open No. 2-159651, parity checks are performed in the vertical and horizontal directions of a plurality of data, thereby facilitating error detection processing. In such a monitoring scheme, a data loss can be detected at most, but no measures can be taken upon detection of a data loss.